The present invention relates to a method of manufacturing a semiconductor device, for example, a technology effective when applied to a method of manufacturing a semiconductor device having a high-breakdown-voltage MISFET and a low-breakdown-voltage MISFET.
Japanese Patent No. 2632101 (Patent Document 1) and Japanese Unexamined Patent Application Publication No. Hei 11 (1999)-177083 (Patent Document 3) disclose a method of manufacturing a semiconductor device having, in source and drain regions of MOSFET thereof, a triple diffusion structure.
Japanese Unexamined Patent Application Publication No. Hei 9 (1997)-275149 (Patent Document 2) discloses a method of manufacturing a MOS transistor having an LDD structure using a double spacer or a thick spacer.